1. Field of the Invention
The present invention relates to a gate array integrated circuit, and more specifically an ECL (emitter coupled logic) gate array integrated circuit including a plurality of internal logic circuit outputs each constituted of an emitter follower circuit output, and a wired logic circuit formed by interconnecting respective emitter follower circuit output terminals.
2. Description of related art
A wired logic has been used in ECL circuits for a long time. For example, a logic sum can be easily obtained by only interconnecting output terminals of emitter follower circuits each constituting an output of a logic circuit. Therefore, the wired logic has become one important means for forming a logic circuit in the ECL gate array integrated circuit (simply called "ECL gate array" hereinafter).
In the prior art, when a wired logic is formed in the ECL gate array, output terminals of a plurality of emitter followers respectively constituting a corresponding number of logic circuit outputs are interconnected by a wiring conductor arbitrarily located among the emitter follower output terminals, and a termination resistor or a constant current source is connected to each of all the emitter follower output terminals, or to only one of the emitter follower output terminals.
In an emitter follower circuit having an emitter connected through a termination resistor to a low level or ground, when the emitter follower circuit outputs a high level potential (H), an emitter follower circuit current flows, which is greatly larger than that flowing when the emitter follower circuit outputs a low level potential (L).
Therefore, in the case that a wired logic is formed by interconnecting among a plurality of emitter follower output terminals by means of a wiring conductor, the emitter follower circuit current flows through the interconnection wiring conductor. However, the interconnection wiring conductor has been distributed or patterned in the shape of a tree structure having a trunk and a plurality of branches divided from the trunk, and if necessary, a plurality of twigs divided from the branches. Each of the emitter follower output terminals is connected to a tip end of a corresponding branch (or twig if exists) of the interconnection wiring conductor.
Here, consider a wired logic circuit formed by interconnecting emitters of four emitter follower transistors (Qa, Qb, Qc and Qd) by an interconnection wiring conductor patterned in the shape of a tree structure having one trunk and a pair of branches divided from each end of the trunk (four branches in total), the respective emitters of each emitter follower transistors being connected to a termination low potential through termination resistors Ra, Rb, Rc and Rd having the same resistance, respectively, and a collector of each emitter follower transistor being connected to a high potential. Assuming that the emitter follower current of 2 mA flows in total, a current of 0.5 mA will flow through each termination resistor.
If all of the four emitter follower transistors are turned on, the emitter follower current flowing through each of the turned-on transistors will flow through the termination resistor directly connected to the emitter of the turn-on transistor, and therefore, no current flows through the interconnection wiring conductor patterned in the shape of a tree structure. However, if only one of the four emitter follower transistors, for example Qa is turned on, the emitter follower current flowing through the only turned-on transistor Qa will flow not only to the termination resistor Ra directly connected to the turned-on transistor Qa but also to the termination resistors Rb, Rc and Rd associated to the other transistors Qb, Qc and Qd. Namely, the emitter follower current flowing from the only turned-on transistor Qa to the termination resistors Rb, Rc and Rd is distributed through the interconnection wiring conductor patterned in the shape of a tree structure.
Specifically, a current of 0.5 mA flows from the emitter of the only turned-on transistor Qa directly through the termination resistor Ra connected to the turned-on transistor Qa, and the remaining current of 1.5 mA flows from the only turned-on transistor Qa through the branch of the interconnection wiring conductor extending from the only turned-on transistor Qa to one end of the trunk of the interconnection wiring conductor. In addition, a current of 1.0 mA flows through the trunk of the interconnection wiring conductor, and a current of 0.5 mA flows through each of the remaining three branches.
Therefore, a current of 1.5 mA flows at maximum through the interconnection wiring conductor. This prior art wired logic will be called a "first prior art wired logic" in this specification.
Here, consider a modification of the above mentioned first prior art wired logic, in which the emitter of only one of the four emitter follower transistors (Qa) is connected to the termination low potential through the termination resistor (Ra), but the emitters of the other emitter follower transistors (Qb, Qc and Qd) are not provided with a termination resistor. In other words, the only termination resistor Ra is connected to the interconnection wiring conductor constituting the wired logic.
In this case, if the emitter follower transistors Qa connected directly to the only termination resistor Ra is turned on, the emitter follower current of 2 mA will flow from the turned-on transistor Qa directly through the only termination resistor Ra, and therefore, no current flows through the interconnection wiring conductor patterned in the shape of a tree structure. However, if one of the emitter follower transistors Qa, Qc and Qd, which are not provided with a termination resistor, is turned on, the emitter follower current of 2 mA will flow from the turned-on transistor to the only termination resistor Ra (directly connected to the emitter of the transistor Qa) through a portion of the interconnection wiring conductor extending between an emitter of the turned-on transistor and the only termination resistor Ra. But, through the other portion of the interconnection wiring conductor, no current flows.
Therefore, a current of 2 mA flows at maximum through the interconnection wiring conductor. This prior art wired logic will be called a "second prior art wired logic" in this specification.
On the other hand, the ECL gate array having output circuits formed of the emitter followers is required to operate at a high speed. Therefore, an impedance of the termination resistor is required to be as small as possible. However, if the impedance of the termination resistor is made small, the emitter follower circuit current will inevitably become large. This can be also applied in the wired logic.
As seen from the above, the wired logic in the emitter follower circuits of the conventional gate array integrated circuits has been constituted by interconnecting N emitter follower output terminals by means of an interconnection wiring conductor patterned in an arbitrary connection pattern such as a tree structure. For example, if the circuit is configured so as to cause an emitter follower circuit current of 2 mA to flow, a current of {2.times.(N-1)/N} mA will flows at maximum through the interconnection wiring conductor constituting the wired logic in the case that each of all the emitter follower output terminals is provided with one termination resistor. In the case that only one of the emitter follower output terminals mutually connected by the interconnection wiring conductor is provided with one termination resistor, a current of 2 mA will flows at maximum through the interconnection wiring conductor constituting the wired logic.
In the ECL gate array, on the other hand, since the interconnection wiring conductor constituting the wired logic is automatically located by means of CAD technique, the interconnection wiring conductors have a uniform width, but different lengths.
In the ECL gate array having the above mentioned restriction, the fact that a large current is caused to flow through the interconnection wiring conductor constituting the wired logic, has the following two disadvantages:
First, since the interconnection wiring conductor itself has a resistance, a voltage shift will occur, which corresponds to a product of the resistance and a current flowing through the interconnection wiring conductor. As a result, a noise margin in the ECL logic circuit is reduced.
For example, if a current of 2 mA flows through the wiring conductor having a wiring resistance of 50.OMEGA., a potential shift of 100 mV will occur.
Secondly, the fact that a large current flows through the wiring conductor having a uniform width, means that an electric current density is high, and therefore, a margin for stress migration is reduced.
Under the above mentioned two disadvantages, the conventional ECL gate array has been constructed to comprise a wired logic formed of an aluminum wiring conductor having a width on the order of 6 .mu.m and a thickness on the order of 1 .mu.m. Accordingly, the wiring resistance of the wiring conductor is about 5.OMEGA. per one millimeter (mm). Therefore, when an emitter follower current of 2 mA is caused to flow, a current density of the wiring conductor becomes 0.33.times.10.sup.5 A/cm.sup.2 in a wired logic arrangement in which only one emitter follower output terminal is connected with a termination resistor. In this case, a magnitude of a potential shift caused by the wiring conductor resistance is within an extent controllable in design of devices.
However, the ECL gate array is recently becoming a large scale more and more, and at the same time, the degree of fineness or microminiaturization is being advanced more and more. As a result, a width of a recent wiring conductor is on the order of 2 .mu.m.
On the other hand, although the microminiaturization of wiring conductors and elements has been advanced, a demand for a high speed operation in the ECL gate array continues or is maintained, and therefore, it is not allowed to reduce the emitter follower circuit current in proportion to the microminiaturization of wiring conductors.
For example, if a wired logic is constructed so as to cause an emitter follower circuit current to flow through a wiring conductor having a width of 2 .mu.m, the wiring resistance becomes about 15 .OMEGA./mm, assuming that the material and the thickness of the wiring conductor do not change. Therefore, the current density of the wiring conductor becomes 1.times.10.sup.5 A/cm.sup.2. Namely, this is a triple of the current density in the wiring conductor having the width of 6 .mu.m.
Considering the stress migration, this would result in deteriorated reliability of the ECL gate array. In addition, if the voltage shift in the wiring conductor is limited below a certain constant value, difficulty in design is increased.